The NAND Flash chips we made in SSDs contain millions of cells with limited number of write cycles. According to the number of data that stored in one cell, we can divided different types of NAND Flash chips, including SLC (Single-Level Cell), MLC (Multi-Level Cell) and TLC (Trinary-Level Cell). The more energy level the NAND Flash chips divided, the larger storage density they are, and the capacity of the products are bigger than the same area of wafer which divided less energy level. As for one chip, when the capacity of NAND Flash is the same, MLC and TLC will have absolute price advantage, but poorer performance.
With the process updating of 2D NAND Flash, the area of each cell is reducing while the output capacity per unit area is increasing and the power dissipation is decreasing. Also, the number of electrons stored in each cell is reducing and can easily lead to data error for electric leakage. Therefore, NAND Flash updates to 3D layout.
3D NAND is in the form of a vertical semiconductor channel, with the GAA structure which forms multi-gate memory cell transistor, it can efficiently reduce interference between the stack. 3D technology not only improves the product performance, but also reduces power consumption.
In order to reduce the risk of losing data when the storage products SMT in high temperature furnace, we set IDA area. It can also improve products reading and writing performance with IDA, reduce the time of first system burn. With Longsys burner, its burning speed can be increased more than 1 times compare to other same type products.
Relative to the Raw NAND Flash has data demand risk when it power-loss, eMMC is optimized for power-loss environments. For the program losing problem of RAW NAND Flash, we use Power-off Protection Algorithm to ensure the system data integrity. Meanwhile, in order to avoid critical data errors, we also carry out Sector level data protection, to exclude write data uncertainty.